In a conventional semiconductor package using a lead frame as a chip carrier, such as quad flat package (QFP) or quad flat non-leaded (QFN) package, a semiconductor chip is mounted on a die pad of the lead frame and electrically connected to the lead frame by a plurality of bonding wires that are bonded to bond pads formed on the chip and corresponding leads of the lead frame. The chip and the bonding wires are encapsulated by an encapsulation body to form the semiconductor package. A surface of the die pad, which is not mounted with the chip, can be exposed from the encapsulation body to facilitate dissipation of heat generated by the chip in the semiconductor package.
In order to protect the electrical performance of a highly integrated chip against noises generated from operation of complex circuits, it is important to improve the grounding quality for the chip during package development. A conventional strategy is to transmit ground signals from the chip to an external device. Referring to FIG. 1, a plurality of ground pads 10 are formed on peripheral area of the die pad 11, and the ground signals can be transmitted from the chip 12 to the ground pads 10 of the die pad 11 via a plurality of grounding wires 13 and then via a plurality of bonding wires 15 to outer leads 16 that are in electrical connection with the external device (not shown). However, in a high-temperature manufacturing process, mismatch in coefficient of thermal expansion (CTE) may lead to delamination between the die pad 11 and the encapsulation body 14. As a result, the grounding wires 13 connected to the die pad 11 are easily broken, thus having poor electrical performance. This situation becomes severe for a semiconductor package with an exposed die pad since the exposed die pad is not firmly encapsulated by the encapsulation body, making delamination between such a die pad and the encapsulation body more possibly occur.
In order to solve the foregoing drawbacks, U.S. Pat. Nos. 5,169,725, 5,237,202, 5,399,809, 5,734,198 and 5,777,265 disclose the use of a multi-layered lead frame, which is modified not forming the grounding wires on the peripheral area of the die pad. The modified technology is to form a ground plane and a power plane in the lead frame, and allow a plurality of grounding wires and power wires to be connected respectively from the ground plane and power plane to the chip. However, such a multi-layered lead frame is complex and cost-ineffective to fabricate, and thus is not commonly utilized in semiconductor packages especially for those sought to be miniaturized in size.
U.S. Pat. No. 5,814,877 discloses a single-layered lead frame. Referring to FIG. 2A and FIG. 2B, a continuous grounding ring 22 is formed and separate from the die pad 21 of the lead frame 20, and the grounding ring 22 is electrically connected to the chip 23 via a plurality of grounding wires 24. Similarly, referring to FIG. 3A and FIG. 3B, U.S. Pat. No. 6,437,427 discloses a lead frame 30 with a grounding ring 32 separate from the die pad 31, allowing the grounding wires 34 to electrically connect the chip 33 to the grounding ring 32 to achieve the grounding effect.
However, the foregoing lead frame with the grounding ring still possesses significant drawbacks. Such a lead frame with grounding ring is relatively complex to fabricate, which is usually formed by stamping and easily results in residual stress on the grounding ring, making the grounding ring deformed during a subsequent high-temperature manufacturing process and thus leading to structural damage and poor electrical performance for the semiconductor package with this lead frame.
Moreover, in the use of the lead frame with grounding ring, a predetermined space between the leads and the die pad must be reserved for the grounding ring, such that wire length required for the connection between the chip and the leads should be increased and thus affects the quality of electrical connection and increases the fabrication cost. In response, a solution is to narrow the grounding ring such that the wire length can be reduced. In this case, however, when the grounding ring undergoes high-temperature manufacturing processes such as die-bond curing, wire-bonding and molding, the continuous structure of the grounding ring causes the thermal stress difficult to be released from the grounding ring, thereby resulting in deformation or “buckle” of the grounding ring as shown in FIG. 4A and FIG. 4B, which is a common phenomenon occurring in a column structure. This “buckle” deformation destroys the planarity of the grounding ring, and the grounding wires are thus uneasily formed on the grounding ring.
Further, during a wire-bonding process, it is not able to use a vacuum socket or clamping equipment, respective for securing the die pad and leads, to hold the grounding ring in position such that the grounding wires cannot be firmly connected to the grounding ring thereby damaging the bonding quality between the grounding wires and the grounding ring.
Referring to FIG. 5A, U.S. Pat. No. 6,396,139 discloses a step-like die pad 40 for increasing the contact area and adhesion between the die pad 40 and the molding compound 41. However, under a high-temperature condition, a surface 40a of the step-like part of the die pad 40 would generate more thermal expansion than another surface 40b of the die pad 40. This uneven thermal expansion causes the die pad 40 to deform and bend downwards as shown in FIG. 5B, thus generating a pulling force to pull and break the grounding wires 42.
Therefore, the problem to be solved here is to provide a semiconductor package with a lead frame, which is cost-effectively fabricated and can improve the grounding effect.